If a partial-word read or write is required, the DMA transfer length register should be programmed to four bytes (or
eight for 64-bit) and the correct bits set in the byte enable bits in the DMA control register. The DMA engine will
transfer a single word, setting the appropriate byte enable bits on both the backend and the PCI interface.
If a non-aligned DMA transfer is required, three separate DMA operations should be performed. The first DMA
transfer should be configured to transfer a single DWORD with just the initial bytes enabled. The second DMA should
transfer the remaining complete DWORDs with all bytes enabled. A third DMA transfer should transfer the final
DWORD with just the remaining bytes enabled. For example, a transfer starting at address 3 and ending at address 12
would require three operations. The first DMA transfer would enable byte 3 only, the second transfer would transfer two
DWORD addresses to bytes 4 through 11, and the third DMA transfer would enable byte 0 and transfer address 12.
CardBus Support
CorePCIF directly supports CardBus functional requirements. Two top-level parameters, CIS_UPPER and
CIS_LOWER, specify the 32-bit configuration space setting for the CIS pointer. CIS_UPPER sets the upper 16 bits,
and CIS_LOWER sets the lower 16 bits.
The CIS address space must be mapped to one of the BARs or the Expansion ROM. It may not be mapped to
configuration space, which means the lower three bits of the CIS pointer (i.e., the lower three bits of CIS_LOWER)
must not be set to '000'. This allows the user to implement the CIS address space as one of the external backend BAR
memory spaces.
When CardBus support is enabled, the IDSEL core input is disabled. CardBus does not require IDSEL to be active for
configuration cycles.
CompactPCI Hot-Swap Support
CorePCIF supports the CompactPCI Hot-Swap PICMG 2.1 R2.0 standard; additional inputs and outputs are
provided to support this standard. When enabled, the core includes the hot-swap capabilities register in the
configuration space and a state machine that implements the hardware connection process defined in the PICMG Hot-
Swap specification. The insertion and extraction sequences are shown in Figure 6-56 on page 103 and Figure 6-57 on
CorePCIF Backend Dataflow
CorePCIF has a very flexible backend interface that supports various transfer rates as well as FIFOs. To decouple the
backend data transfers from the PCI transfers, CorePCIF implements an eight-stage FIFO for each BAR. During
normal operation, the FIFO stores up to four data words, the remaining four locations being used for the FIFO recovery
mechanism. This is implemented using FPGA memory resources in all families except SX-A, RTSX-S, and RTAX-S.
Burst Transfers
CorePCIF is capable of bursting data from the PCI bus to the backend or vice versa. During transfers to the backend,
the WR_BE_RDY and WR_BE_NOW signals are used to control the dataflow. When the backend asserts
WR_BE_RDY, the core is allowed to write data to the backend by asserting WR_BE_NOW. A separate
WR_BE_NOW signal is provided for each byte.
For transfers from the backend, RD_STB_IN and RD_STB_OUT control the dataflow. When both of these signals are
active, data is transferred from the backend into the core.
20
v4.0
相关PDF资料
COREU1LL-AR IP MODULE COREU1LL
COREU1PHY-AR IP MODULE COREU1PHY
CORR-8BIT-XM-UT2 SITE LICENSE IP CORRELATOR XP
CP2-GSA-L CONN SHIELD LOWER TYPE A 22
CP2-HSA110-1 CONN SHROUD CPCI 2MM TYPE A 22
CP2-HSC055-4 CONN SHROUD CPCI 2MM TYPE C 11
CP2-K3567-SR-F COMPACT PCI - MISC
CP2105EK KIT EVAL FOR CP2105
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